Selectable capacitor banks and charge redistribution using Successive Approximation Registers (SAR) are often used to perform analog-to-digital conversion. These successive approximation ADCs provide good resolution, an ability to asynchronously sample an input signal, and a relatively small amount of circuitry when compared to other ADC techniques. However, successive approximation ADCs may be susceptible to errors due to a broad range of voltages that can be applied to inputs of the comparison circuitry. The comparison circuitry must be capable of accurately comparing very small differences between input signals and at the same time, accurately compare input signals with relatively high voltage differences.
One source of errors in successive approximation ADCs is a time-dependent and voltage-dependent threshold shift in Metal Oxide Semiconductor (MOS) transistors used in the comparison circuitry. This threshold shift is often referred to as a hysteresis effect. The relatively high voltages that may be placed on inputs of the comparison circuitry during early stages of a SAR process can cause large overdrive of comparator inputs, which may result in a significant threshold shift effect that can cause errors in the ADC.
One proposal for addressing the threshold shift effect is disclosed in U.S. Pat. No. 5,675,340 to Hester et al., which includes a coarse ADC added to a traditional SAR ADC to reduce the voltages imposed on a comparator in the traditional SAR ADC.
Another proposal for addressing the threshold shift effect is disclosed in U.S. Pat. No. 5,006,853 to Kiriaki et al., which uses a coarse comparator for higher voltages and a fine comparator for lower voltages so that the fine comparator is not subject to the high voltages that might cause errors due to the hysteresis effect.
However, these proposals include complex control logic, considerable additional circuitry, or combinations thereof. The inventors have appreciated that there is a need to provide new apparatuses and methods that simplify and improve error reduction in ADCs by limiting a voltage range applied to a comparator.